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| DATA SHEET MOS INTEGRATED CIRCUIT PD16314 DOT CHARACTER VFD CONTROLLER/DRIVER DESCRIPTION The PD16314 is a VFD controller/driver capable of displaying a dot matrix VFD. It has 80 anode outputs and 24 grid outputs. A single PD16314 can display up to 16C x 2L, 20C x 2L, or 24C x 2L. The PD16314 has character generator ROM in which 248 x 5 x 8 dot characters are stored. FEATURES * Dot matrix VFD controller/driver * Capable of driving anodes for cursor display (48 units) * 80 x 8 bits display RAM incorporated * Capable of alphanumeric and symbolic display through internal ROM (5 by 8 dots) 240 characters plus 8 user-defined characters * Display contents 16 columns by 2(1) rows + 32(16) cursors, 20 columns by 2(1) rows + 40(20) cursors, or 24 columns by 2(1) rows + 48(24) cursors. * Parallel data input/output (switchable between 4 bits and 8 bits) or serial data input/output can be selected. * On-chip oscillator * Custom ROM supported ORDERING INFORMATION Part Number Package 144-PIN PLASTIC LQFP(FINE PITCH)(20x20), Standard ROM (ROM code: 001) 144-PIN PLASTIC LQFP(FINE PITCH)(20x20), Standard ROM (ROM code: 002) PD16314GJ-001-8EU PD16314GJ-002-8EU The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S13231EJ1V0DS00 (1st edition) Date Published March 2000 NS CP(K) Printed in Japan The mark * shows major revised point. (c) 1997 2 Remark TESTOUT OSCIN OSCOUT XOUT SDO SLK /CL LE 3 OSCILATIOR ADDRESS COUNTER 7 8 I/O B U F F E R INSTRUCTION REGISTER 7 8 INSTRUCTION DECORDER DISPLAY DATA RAM (DDRAM) 80 x 8 bits 8 CURSOR BLINK CONTROL CIRCUIT 8 4 7 CHARACTER GENERATOR DB4 to DB7 4 RAM (CGRAM) 8 x 5 x 8 bits 8 CHARACTER GENERATOR ROM (CGROM) 248 x 5 x 8 bits ANODE SIGNAL DRIVER 80 /RESET RESET CIRCUIT 5 MPU DS0 DS1 DLS R,L1 R,L2 PARALLEL TO SERIAL DATA CONVERTER 80-BIT SHIFT REGISTER 5 80-BIT LATCH 80 80 A1 to A80 7 7 TIMING GENERATOR 24 24-BIT SHIFT REGISTER 24 GRID SIGNAL DRIVER 24 G1 to G24 1. BLOCK DIAGRAM /xxx indicates active low signals. TEST IM /CS RS,STB Data Sheet S13231EJ1V0DS00 R,/W(/WR) E(/RD),SCK 8 DATA REGISTER 8 SI,SO DB0 to DB3 PD16314 VDD1 VDD2 VSS1 VSS2 PD16314 2. PIN CONFIGURATION (Top View) N.C. A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 N.C. 108 109 A70 A69 A68 A67 A66 A65 A64 A63 A62 A61 A60 A59 A58 A57 A56 A55 A54 A53 A52 A51 A50 A49 A48 A47 A46 A45 A44 A43 A42 A41 A40 A39 A38 A37 A36 A35 73 72 144 1 37 36 N.C. A34 A33 A32 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 N.C. Remark Use all power supply pins. Leave N.C. pins open. VDD2 VSS2 VDD1 XOUT OSCOUT OSCIN /RESET TEST DLS DS1 DS0 R,/W(/WR) RS,STB E(/RD),SCK SI,SO DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 IM MPU /CS R,L1 R,L2 /CL LE SDO SLK TESTOUT VSS1 VSS2 VDD2 Data Sheet S13231EJ1V0DS00 3 PD16314 3. PIN FUNCTIONS 3.1 Power System Pin Symbol VDD1 VSS1 VDD2 VSS2 Pin Name Logic power supply pin Logic ground pin VFD driving power supply pin VFD driving ground pin Pin No. 3 34 1,36 2,35 I/O Output Description Power supply for logic Ground pin for logic Power supply for VFD driving circuit Ground pin for VFD driving 4 Data Sheet S13231EJ1V0DS00 PD16314 3.2 Logic system (Microprocessor Interface) Pin Symbol RS,STB Pin Name Register select/strobe Pin No. 13 I/O I Output Description When Parallel data transfer is selected, this pin is Register select. L: Select instruction register(IR). H: Select data register(DR). When serial data transfer mode is selected, this pin is the strobe input. Data can be input when this signal goes L. Command processing is performed at the rising edge of this signal. /CS E(/RD), SCK Chip select Enable(read)/shift clock 26 14 I I When this pin is L, this device is active. When M68 parallel data transfer mode is selected (E), this pin is enabled. Data is written at the falling edge. When i80 parallel data transfer selected (/RD), this pin is a read-enable pin. When this pin is L, data is output to the data bus. When serial data transfer is selected, this pin is the shift clock input. Data is written at the rising edge. R,/W(/WR) Read/write signal (write) 12 I When M68 parallel data transfer mode is selected (R,/W), this pin is the data transfer select pin. L: Write H: Read When i80 parallel data transfer mode is selected (/WR), this pin is written a write-enable pin. Data is written at rising edge of this signal. When serial data transfer mode is selected this pin is fixed to H or L. SI,SO Serial I/O 15 I/O CMOS3-states When serial data transfer mode is selected, this pin is used as an I/O pin. When parallel data transfer mode is selected, this pin is fixed to H or L. DB0 to DB7 DB0 - DB7 Parallel data I/O 16 to 23 I/O CMOS3-states When parallel data transfer mode is selected, these pins are used as I/O pins. When 4-bits transfer mode is selected, DB4 to DB7 are used. Data is transferred starting from the most significant bit (MSB) and stored sequentially. /RESET Reset 7 I L: Initializes all the internal registers and commands. Anode and grid outputs are fixed to VSS2. Data Sheet S13231EJ1V0DS00 5 PD16314 3.3 Logic System (Other Logic) Pin Symbol OSCIN OSCOUT XOUT DS0 DS1 Oscillator output Duty selector Pin Name Oscillator pin Pin No. 6 5 4 11 10 I CMOS I/O Output Description The resister for determining the oscillation frequency is externally attached to this pin. Oscillator signal output pin. Sets the duty ratio. The duty ratio is determined by the number of grids. The relationship between the duty ratio and these pins is shown in 4 DUTY RATIO SETTING. IM Interface select 24 I Selects the interface mode: Serial transfer or parallel transfer. L: Selects serial data transfer H: Selects parallel data transfer (In Parallel data transfer mode, the word length differs depending on the instruction.) MPU Interface select 25 I Selects the interface mode: i80-type CPU mode or M68-type CPU mode. L: Selects i80-type CPU mode. H: Selects M68-type CPU mode. DLS Display line select 9 I Selects the number of display lines at power ON reset or reset. L: Selects 1 line (N Note = 0) = 1) H: Selects 2 lines (N R,L1 Anode output select 27 I Note Sets the anode outputs. The Ox pins are set by these pins. R,L2 28 The relationship between Ox and Ax (anode) is shown in 5 ANODE SETTING. TEST Test pin 8 I A pin for testing the IC. L or open: Normal operation mode H: Test mode TESTOUT Test pin 33 O A pin for testing the IC. Leave this pin open. Note N: Display line selection flag for function setting command. 3.4 Logic System (External Extension Driver) Pin Symbol SDO SLK /CL Pin Name Serial data output Serial clock output Clear signal Pin No. 31 32 29 I/O O O O Output CMOS CMOS CMOS Description Serial data output for extension grid driver. Shift clock pulse for extension grid driver. Clear signal for extension grid driver. The signal is active low. The grid data stored in the latch of the extension driver is output when this signal is H. If this signal is L, the extension driver outputs L. LE Latch enable 30 O CMOS Latch enable signal for extension grid driver. 6 Data Sheet S13231EJ1V0DS00 PD16314 3.5 Output Pins Pin Symbol G1 - G24 A1 - A80 (O1 - O80) Pin Name Grid output Anode output Pin No. Note Note I/O O O Output CMOS CMOS Description Grid signal output pins. Anode signal output pins. Note Refer to 4 DUTY RATIO SETTING. Data Sheet S13231EJ1V0DS00 7 PD16314 4. DUTY RATIO SETTING The duty ratio of the PD16314 is set by DS0 and DS1 as shown in Table 4-1 below. - Table 4-1. Duty Ratio Setting - DS0 L L H H DS1 L H L H Duty ratio 1/16 (# of grids = 16) 1/20 (# of grids = 20) 1/24 (# of grids = 24) 1/40 (# of grids = 40) Note Note When to set to 1/40 duty mode, the external extension grid driver can be used. 5. ANODE SETTING The anode pins are set by R,L1 and R,L2 as shown in Table 5-1 below. - Table 5-1. Anode Setting: 2 Line Display (N=1) - R,L1 L L H H R,L2 L H L H Table 5-2 Table 5-3 Table 5-3 Table 5-4 Table No. 8 Data Sheet S13231EJ1V0DS00 PD16314 Table 5-2. Anode Pin Layout (When R,L1 = L, R,L2 = L) - No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VDD2 VSS2 VDD1 XOUT OSCOUT OSCIN /RESET TEST DLS DS1 DS0 R,/W(/WR) RS,STB E(/RD),SCK SI,SO DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 IM MPU /CS R,L1 R,L2 /CL LE SDO SLK TESTOUT VSS1 VSS2 VDD2 Name No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 N.C. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 N.C. Name No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 Name No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 N.C. A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 N.C. Name Data Sheet S13231EJ1V0DS00 9 PD16314 Table 5-3. Anode Pin Layout (When R,L1 = L, R,L2 = H) - No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VDD2 VSS2 VDD1 XOUT OSCOUT OSCIN /RESET TEST DLS DS1 DS0 R,/W(/WR) RS,STB E(/RD),SCK SI,SO DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 IM MPU /CS R,L1 R,L2 /CL LE SDO SLK TESTOUT VSS1 VSS2 VDD2 Name No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 N.C. A40 A39 A38 A37 A36 A35 A34 A33 A32 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 N.C. Name No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 A6 A5 A4 A3 A2 A1 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 Name No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 N.C. A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 N.C. Name 10 Data Sheet S13231EJ1V0DS00 PD16314 Table 5-4. Anode Pin Layout (When R,L1 = H, R,L2 = L) - No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VDD2 VSS2 VDD1 XOUT OSCOUT OSCIN /RESET TEST DLS DS1 DS0 R,/W(/WR) RS,STB E(/RD),SCK SI,SO DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 IM MPU /CS R,L1 R,L2 /CL LE SDO SLK TESTOUT VSS1 VSS2 VDD2 Name No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 N.C. A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 N.C. Name No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 A75 A76 A77 A78 A79 A80 A40 A39 A38 A37 A36 A35 A34 A33 A32 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Name No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 N.C. A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 N.C. Name Data Sheet S13231EJ1V0DS00 11 PD16314 Table 5-5. Anode Pin Layout (When R,L1 = H, R,L2 = H) - No. Name VDD2 VSS2 VDD1 XOUT OSCOUT OSCIN /RESET TEST DLS DS1 DS0 R,/W RS,STB E(/RD),SCK SI,SO DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 IM MPU /CS R,L1 R,L2 /CL LE SDO SLK TESTOUT VSS1 VSS2 VDD2 No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 N.C. A80 A79 A78 A77 A76 A75 A74 A73 A72 A71 A70 A69 A68 A67 A66 A65 A64 A63 A62 A61 A60 A59 A58 A57 A56 A55 A54 A53 A52 A51 A50 A49 A48 A47 N.C. Name No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 A46 A45 A44 A43 A42 A41 A40 A39 A38 A37 A36 A35 A34 A33 A32 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Name No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 N.C. A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 N.C. Name * * * * * * 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 12 Data Sheet S13231EJ1V0DS00 PD16314 Table 5-6. Anode Setting: 1 Line Display (N=0) - R,L1 Don't care Don't care R,L2 L H Table 5-7 Table 5-8 Table No. Table 5-7. Anode Pin Layout (When R,L2 = L) - No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VDD2 VSS2 VDD1 XOUT OSCOUT OSCIN /RESET TEST DLS DS1 DS0 R,/W RS,STB E(/RD),SCK SI,SO DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 IM MPU /CS R,L1 R,L2 /CL LE SDO SLK TESTOUT VSS1 VSS2 VDD2 Name No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 N.C. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 N.C. Name No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 A35 A36 A37 A38 A39 A40 Unused Name No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 N.C. N.C. Unused Name Data Sheet S13231EJ1V0DS00 13 PD16314 Table 5-8. Anode Pin Layout (When R,L2 = H) - No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VDD2 VSS2 VDD1 XOUT OSCOUT OSCIN /RESET TEST DLS DS1 DS0 R,/W RS,STB E(/RD),SCK SI,SO DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 IM MPU /CS R,L1 R,L2 /CL LE SDO SLK TESTOUT VSS1 VSS2 VDD2 Name No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 N.C. A40 A39 A38 A37 A36 A35 A34 A33 A32 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 N.C. Name No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 A6 A5 A4 A3 A2 A1 Unused Name No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 N.C. N.C. Unused Name 14 Data Sheet S13231EJ1V0DS00 PD16314 6. VFD DISPLAY The PD16314 can display 24 characters x 2 lines, and a VFD can be connected as shown in the figure below. Figure 6-1. VFD Display - A1 A40 A41 PD16314 A80 G1 G2 G24 A1 A5 A6 A10 A71 A75 A76 A80 Data Sheet S13231EJ1V0DS00 15 PD16314 7. BLOCK FUCTIONS 7.1 CPU Interface The PD16314 is provided with a 4-or 8-bit parallel interface and a serial interface. The interface mode is set by the IM pin. IM = "L": Serial data transfer IM = "H": Parallel data transfer Table 7-1. CPU Interface - IM L H /CS /CS /CS RS,STB STB RS E(/RD),SCK SCK E(/RD) R,/W(/WR) MPU SI,SO SI,SO DBn Note R,/W(/WR) Note MPU Note DBn Note Note Fix this pin to H or L. 7.2 Registers (IR, DR) The PD16314 has two 8-bit registers: an instruction register (IR) and a data register (DR). The IR stores instruction codes, such as display clear and cursor shift, and address information for display data RAM (DDRAM) and character generator RAM (CGRAM). The IR can only be written to from the MPU. The DR temporarily stores the data to be written or read from DDRAM or CGRAM Table 7-2. Register Selection (IR, DR) - Common RS L L H H M68 R,/W L H L H /RD H L H L i80 /WR L H L H IR data is written as an internal operation (display clear, etc.) Data is read to the busy flag (DB7) and address counter (DB6 to DB0) DR data is written (DR DDRAM, CGRAM). DR data is read (DDRAM, CGRAM DR). Function 7.3 Busy Flag (Read BF Flag) L is always output for busy flag data (DB7). 7.4 Address Counter (AC) The address counter(AC) assigns addresses to both DDRAM and CGRAM. When an instruction address is written the IR, the address information is sent from the IR to the AC. Selection of either DDRAM or CGRAM is also determined concurrently by the instruction. After writing to (reading from) DDRAM or CGRAM, the AC is automatically incremented (+1) . The AC contents are output to DB0 to DB6 when RS = L and R,/W = H (Refer to Table 7-2. Register Selection (IR,DR).). - 16 Data Sheet S13231EJ1V0DS00 PD16314 7.5 Display Data RAM (DDRAM) Display data RAM (DDRAM) stores display data displayed in 8-bit character codes. Its capacity is 80 x 8 bits, or 80 characters. The area in DDRAM that is not used for display can be used as general data RAM. Refer to 7.5.1 1-line display (N = 0), 7.5.2 2-line display (N = 1) for the relationship between the DDRAM address and the position on the VFD. The DDRAM address (ADD) is set in the address counter (AC) as hexadecimal. Figure 7-1. DDRAM Address High-order bits Low-order bits AC4 AC3 AC2 AC1 AC0 AC AC6 AC5 Hexadecimal Example : DDRAM address "26" 0 1 2 0 0 Hexadecimal 1 6 1 0 7.5.1 1-line display (N = 0) Figure 7-2. 1-Line Display - Display position (Digit) DDRAM address (Hexadecimal) 1 00 2 01 3 02 4 03 5 04 6 05 ....... ....... 79 4E 80 4F When there are fewer than 80 display characters, the display begins at the head position. For example, if using only one PD16314, 24 characters are displayed. When a display shift operation is executed, the DDRAM address shifts. Refer to Figure 7-3. Example of 1-line/24-Character Display. Figure 7-3. 1-line by 24 Characters Display Example - Display position (Digit) DDRAM address (Hexadecimal) Left shift 01 02 03 04 05 06 ..... 17 18 1 00 2 01 3 02 4 03 5 04 6 05 ..... ..... 23 16 24 17 Right shift 4F 00 01 02 03 04 ..... 15 16 Data Sheet S13231EJ1V0DS00 17 PD16314 7.5.2 2-line display (N = 1) Figure 7-4. 2-Line Display - Display position (Digit) DDRAM address (Hexadecimal) 1 00 40 2 01 41 3 02 42 4 03 43 5 04 44 6 05 45 ....... ....... ....... 39 26 66 40 27 67 When the number of display character is less than 40 x 2 lines, the 2 lines are displayed from the head. The first line end address and the second line start address are not consecutive. For example, if using only one PD16314, 24 characters x 2 lines are displayed. When a display shift operation is executed, the DDRAM address shifts. Refer to Figure 7-5. Example of 2-Line/24-Character Display. Figure 7-5. Example of 2-Line/24-Character Display - Display position (Digit) DDRAM address (Hexadecimal) 1 00 40 2 01 41 3 02 42 4 03 43 5 04 44 6 05 45 ....... ....... ....... 23 16 56 24 17 57 Left shift 01 41 02 42 03 43 04 44 05 45 06 46 ....... ....... 17 57 18 58 Right shift 27 67 00 40 01 41 02 42 03 43 04 44 ....... ....... 15 55 16 56 For 40 characters x 2 lines display, the PD16314 can be extended using one 16-output grid extension driver. When a display shift operation is executed, the DDRAM address shifts. Refer to Figure 7-6. Example of - 2-Line/40-Character Display. Figure 7-6. Example of 2-Line/40-Character Display - Display position (Digit) DDRAM address (Hexadecimal) 1 00 40 2 01 41 3 02 42 4 03 43 23 16 56 24 17 57 25 18 58 39 26 66 40 27 67 Left shift 01 41 02 42 03 43 04 44 17 57 18 58 19 59 27 57 00 40 Right shift 27 67 00 40 01 41 02 42 15 55 16 56 17 57 25 65 Extension driver display 26 66 PD16314 display 18 Data Sheet S13231EJ1V0DS00 PD16314 7.6 Character Generator ROM (CGROM) CGROM, which is ROM for generating character patterns of 5 x 8 dots from 8-bit character codes, generates 240 types of character patterns. The character codes are shown on the following page. The character codes 00H to 0FH are allocated to the CGRAM. Data Sheet S13231EJ1V0DS00 19 PD16314 Figure 7-7. Character Code Table 1 (ROM code: 001) - 0 CG RAM (0) 1 2 3 4 5 6 7 8 9 A B C D E F XXXX0000 0 XXXX0001 1 CG RAM (1) XXXX0010 2 CG RAM (2) CG RAM (3) XXXX0011 3 XXXX0100 4 CG RAM (4) XXXX0101 5 CG RAM (5) XXXX0110 6 CG RAM (6) CG RAM (7) XXXX0111 7 XXXX1000 8 CG RAM (0) CG RAM (1) CG RAM (2) XXXX1001 9 XXXX1010 A XXXX1011 B CG RAM (3) XXXX1100 C CG RAM (4) XXXX1101 D CG RAM (5) XXXX1110 E CG RAM (6) CG RAM (7) XXXX1111 F 20 Data Sheet S13231EJ1V0DS00 PD16314 Figure 7-8. Character Code Table 2 (ROM code: 002) - 0 CG RAM (0) 1 2 3 4 5 6 7 8 9 A B C D E F XXXX0000 0 XXXX0001 1 CG RAM (1) XXXX0010 2 CG RAM (2) CG RAM (3) XXXX0011 3 XXXX0100 4 CG RAM (4) XXXX0101 5 CG RAM (5) XXXX0110 6 CG RAM (6) CG RAM (7) XXXX0111 7 XXXX1000 8 CG RAM (0) XXXX1001 9 CG RAM (1) CG RAM (2) XXXX1010 A XXXX1011 B CG RAM (3) XXXX1100 C CG RAM (4) XXXX1101 D CG RAM (5) CG RAM (6) XXXX1110 E XXXX1111 F CG RAM (7) Data Sheet S13231EJ1V0DS00 21 PD16314 7.7 Character Generator RAM (CGRAM) With character generator RAM (CGRAM), the user can rewrite character patterns by program. For 5 x 8 dots, 8character patterns can be written. Character codes 00H to 07H and 08H to 0FH have the same CGRAM contents. Refer to Figure 7-9 for the relationship between the CGRAM address and data and display patterns. Areas - that are not used for display can be used as general data RAM. Figure 7-9. Relationship between the CGRAM Address, Character Code (DDRAM) - and 5 x 7 (With Cursor) Dot Character Patterns (CGRAM) Character code (DDRAM data) D7 D6 D5 D4 D3 D2 D1 D0 A5 CGRAM address A4 A3 A2 A1 A0 D7 D6 D5 CGRAM data D4 D3 D2 D1 D0 High-order bits 0 0 0 0 x Low-order bits High-order bits Low-order bits 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 High-order bits x x x 1 1 1 1 1 1 1 0 x x x 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 Low-order bits 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 Cursor position Cursor position Character pattern (0) 0 0 0 0 x 0 0 1 0 0 1 0 0 0 0 1 1 1 1 Character pattern (1) 0 0 0 0 x 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x x x 0 1 1 1 1 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 1 Cursor position Character pattern (7) Remarks 1. x: Don't care. 2.Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types). 3.CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and its display is formed by a logical OR with the cursor specification. If the 8th line data is made 0, the display is determined by the cursor specifiaction. If the 8th line data is 1, the 8th line will light up regardless of the cursor presence. 4.1 for CGRAM data corresponds to display selection and 0 to non selection. 22 Data Sheet S13231EJ1V0DS00 PD16314 7.8 Timing Generator The timing generator generates timing signals for the operation of internal circuits such as DDRAM, CGRAM and CGROM. The RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interference. Therefore, when writing data to DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than the display area. 7.9 VFD Driver Circuit The VFD driver circuit consists of 24 grid signal drivers and 80 anode signal drivers. When the character font and number of digits are selected, the required grid signal drivers automatically output drive waveforms. 7.10 Cursor/Blink Control Circuit The cursor/blink control circuit generates the cursor or character blink. The cursor or blink is valid at the digit located at the display data RAM (DDRAM) address set in the address counter (AC). For example, when the address counter is 08H, the cursor position is displayed at DDRAM address 08H. Figure 7-10. Cursor/Blink Control - AC6 AC 0 AC5 0 AC4 0 AC3 1 AC2 0 AC1 0 AC0 0 For 1-line display Display position (Digit) DDRAM address (Hexadecimal) Cursor position For 2-line display Display position (Digit) DDRAM address (Hexadecimal) 1 00 40 2 01 41 3 02 42 4 03 43 5 04 44 6 05 45 7 06 46 8 07 47 9 08 48 10 09 49 11 0A 4A 12 0B 4B 1 00 2 01 3 02 4 03 5 04 6 05 7 06 8 07 9 08 10 09 11 0A 12 0B Cursor position Data Sheet S13231EJ1V0DS00 23 PD16314 8. INTERFACING WITH CPU (DATA TRANSFER) * 8.1 Parallel Data Transfer M68 (IM = H, MPU = H) This IC can interface (data transfer) with the CPU in 4 or 8 bits (M68 interface: IM = H, MPU = H). However, because the internal registers consist of 8 bits, when transfering data in 4 bits DB4 to DB7 must be used twice. When using 4-bit parallel data transfer, maintain the DB0 to DB3 pins at H or L. The transfer order is the higher 4 bits first (D4 to D7) followed by the lower 4 bits (D0 to D3). Figure 8-1. Parallel Data Transfer M68 (IM = H, MPU = H) - (a) 4-bit data transfer (M68) RS R,/W E DB7 IR7 IR3 IR7 IR3 BF = "0" IR3 D7 D3 DB6 IR6 IR2 IR6 IR2 IR6 IR2 D6 D2 DB5 IR5 IR1 IR5 IR1 IR5 IR1 D5 D1 DB4 IR4 IR0 IR4 IR0 IR4 IR0 D4 Write data D0 Write instruction Write instruction Read instruction (b) 8-bit data transfer (M68) RS R,/W E DB7 IR7 IR7 BF = "0" D7 DB6 IR6 IR6 IR6 D6 DB0 IR0 Write instruction IR0 Write instruction IR0 Read instruction D0 Write data 24 Data Sheet S13231EJ1V0DS00 PD16314 8.2 Parallel Data Transfer i80 (IM = H, MPU = L) When IM = H, MPU = L is set, i80 is selected. In the PD16314, each time data is sent to and from the CPU, the data is retained the bus holder attached to internal data bus, and is written to the display data RAM by the next data write cycle. When the CPU reads the contents of the display data RAM, the read data is retained in the bus holder for the first data read cycle (dummy), and is read out on the system bus at the next data read cycle. There are certain restrictions in the read sequence of this display data RAM. Be advised that data of the specified address is not generated by the read instruction issued immediately after the address setting. This data is generated when the data is read of the second time. Thus, a dummy read is required following an address setting or write cycle. This relationship is shown in following figure. Figure 8-2. Parallel Data Transfer i80 (IM = H, MPU = L) - Writing MPU /WR Data N N+1 N+2 N+3 Internal timing Latch BUS holder Write signal N N+1 N+2 N+3 Reading MPU /WR /RD Data N N n n+1 Internal timing Address preset Read signal Column address BUS holder Address set #n Preset N Increment N+1 N+2 N n n+1 n+2 Dummy read Data read #n Data read #n+1 Data Sheet S13231EJ1V0DS00 25 PD16314 8.3 Serial Data Transfer This IC can interface (data transfer) with the CPU in serial. Data can be written when STB = L. The first byte is the start byte. The IR or the DR is selected by the RS bit(bit 6) and data write or read by R,/W(bit 5 = 0). The next first bytes are instructions on data. When data is read, whether to read the busy flag + address counter (AC6 to AC0) or to read the data written in DDRAM or CGRAM is chosen by the start byte input first. Data is output at the falling edge of the shift clock. Figure 8-3. Serial Data Transfer - Data write STB 1 SCK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SI "1" "1" "1" "1" "1" R,W RS "0" D7 D6 D5 D4 D3 D2 D1 D0 Synchronous bits Start byte Data read Instruction/Data STB Wait time : tWAIT 1 s 1 SCK BF "0" 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 SI,SO "1" "1" "1" "1" "1" R,W RS "0" IR6 IR5 IR4 IR3 IR2 IR1 IR0 Synchronous bits Start byte Read data 26 Data Sheet S13231EJ1V0DS00 PD16314 9. INSTRUCTIONS Instruction Clear display RS 0 R,/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1 Description Clears the entire display, and sets the DDRAM address to 00H. Cursor home 0 0 0 0 0 0 0 0 1 x Sets the DDRAM address to 00H. Also returns the display being shifted to the original position. DDRAM contents remain unchanged. Entry mode set 0 0 0 0 0 0 0 1 I/D S Sets the cursor direction and specifies display shift. These operations are performed during writing/reading data. Display ON/OFF 0 0 0 0 0 0 1 D C B Turns the entire display ON/OFF(D), the cursor ON/OFF(C), and sets the cursor blink at the character position(B). Cursor or display shift 0 0 0 0 0 1 S/C R/L x x Shifts the display or cursor. Maintains DDRAM contents. Function set 0 0 0 0 1 DL N x BR1 BR0 Sets the data length (parallel data transfer) and number of lines CGRAM address set 0 0 0 1 ACG Set the address of CGRAM. After that, CGRAM data is transferred. DDRAM address set 0 0 1 AD D Set the address of DDRAM. After that, DDRAM data is transferred. Read busy flag & address 0 1 BF='0' AC Reads the busy flag (BF) and address counter. BF o always outputs `0'. Write data to CGRAM or DDRAM Read data from CGRAM or DDRAM 1 1 Read DR data 1 0 Write data Writes data to CGRAM or DDRAM. Reads data from CGRAM or DDRAM. Data Sheet S13231EJ1V0DS00 27 PD16314 Remarks 1. I/D = 1: Increment I/D = 0: Decrement S = 1: Display shift enabled S = 0: Cursor shift enabled S/C = 1: Display shift S/C = 0: Cursor shift R/L = 1: Shift to the right R/L = 0: Shift to the left DL = 1: 8 bits DL = 0: 4 bits N = 0: 1 Line N = 1: 2 Lines BR1,BR0 = 00: 100% 01: 75% 10: 50% 11: 25% 2. X: Don't care DDRAM: Display Data RAM CGRAM: Character Generator RAM ACG: CGRAM address ADD: DDRAM address AC: Address counter 28 Data Sheet S13231EJ1V0DS00 PD16314 10. INSTRUCTION DESCRIPTION 10.1 Clear Display RS Code 0 R,/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1 This instruction: (1) Writes to 20H (Space code) all locations in display data RAM (DDRAM) (2) Sets the address counter (AC) to the DDRAM address 00H. (3) Returns the display Shift to 0. (4) If cursor is displayed, the cursor is moved to the far left edge of the top line (upper line). After reset: DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1 10.2 Cursor Home RS Code 0 R,/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 x This instruction: (1) Sets the address counter (AC) to the DDRAM address 00H. (2) Returns the display Shift to 0. (3) If cursor is displayed, the cursor is held at the far edge of left the top line (upper line). Data Sheet S13231EJ1V0DS00 29 PD16314 10.3 Entry Mode RS Code 0 R,/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 S The I/D determines the way in which the contents of address counter are modified after every access to DDRAM or CGRAM. I/D = 1: Address counter incremented after access to DDRAM or CGRAM. I/D = 0: Address counter decremented after access to DDRAM or CGRAM. The S bit determines a display shift whether or a cursor shift occurs after each write or read to/from DDRAM. S = 1: Display shift enabled. S = 0: Cursor shift enabled. The direction in which the display is shifted is the opposite to that of the cursor. For example, if S = 0 and I/D = 1, cursor would shift one character to the right after a CPU write to DDRAM. However if S = 1 and I/D = 1, the display would shift one character to the left and cursor would maintain its position on the panel. Note that the cursor is shifted in the direction selected by I/D when DDRAM is read, irrespective of the value of S. Similarly reading and writing CGRAM always causes the cursor to shift. Table 10-1. Cursor Move and Display Shift by Entry Mode Setting - I/D 0 1 0 S 0 0 1 After Writing DDRAM Data Cursor moves one character to the left. Cursor moves one character to the right. Display shifts one character to the right without cursor moving. 1 1 Display shifts one character to the left without cursor moving. Cursor moves one character to the right. After Reading DDRAM Data Cursor moves one character to the left. Cursor moves one character to the right. Cursor moves one character to the left. After reset: DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 1 DB0 0 30 Data Sheet S13231EJ1V0DS00 PD16314 10.4 Display ON/OFF RS Code 0 R,/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 B This instruction controls various features of the display. D = 1: Display on, D = 0: Display off. C = 1: Cursor on, C = 0: Cursor off. B = 1: Blink on, B = 0: Blink off. Blinking is achieved by alternating between a normal and all-on display of a character. The cursor blinks with a frequency of 1 Hz and a duty of 50 %. Blink (1 Hz) Cursor line After reset: DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 0 DB1 0 DB0 0 10.5 Cursor or Display Shift RS Code 0 R,/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 S/C DB2 R/L DB1 x DB0 x This instruction shifts the display and/or moves the cursor, one character to the left or right, without reading or writing to DDRAM. The S/C bit selects movement of the cursor or movement of both the cursor and display. S/C = 1: Shifts both the cursor and display. S/C = 0: Shifts only the cursor. The R/L bit selects whether to move the display and/or cursor to the left or right. R/L = 1 : Shift one character to the right. R/L = 0 : Shift one character to the left. Table 10-2. Cursor or Display Shift - S/C 0 0 1 1 R/L 0 1 0 1 Cursor Moves one character to the left. Moves one character to the right. Moves one character to the left with the display. Moves one character to the right with the display. No shift. No shift. Shifts one character to the left. Shifts one character to the right. Display Data Sheet S13231EJ1V0DS00 31 PD16314 10.6 Function Setting RS Code 0 R,/W 0 DB7 0 DB6 0 DB5 1 DB4 DL DB3 N DB2 x DB1 BR1 DB0 BR0 This instruction sets the data length of the data bus line (when using the parallel interface, IM = H), the number of display lines and the brightness adjustment. This instruction initializes the system, and must be the first instruction executed after power-on. DL = 1: 8-bit CPU interface using DB7 to DB0 DL = 0: 4-bit CPU interface using DB7 to DB4 N = 0: Selects 1-line display (using anode outputs A1 to A40. A41 to A80 are fixed to low .). N = 1: Selects 2-line display (using anode outputs A1 to A80). The BR1, BR0 flags control the brightness of VFD by adjusting the to pulse width of the anode outputs as follows. tDSP 200 s, tBLK 10 s BR1 0 0 1 1 BR0 0 1 0 1 Brightness 100 % 75 % 50 % 25 % T tDSP tp tp tDSP x 1.00 tDSP x 0.75 tDSP x 0.50 tDSP x 0.25 An tBLK tBLK G1 Gn Remark n: Number of grids, T = n x (tDSP + tBLK) After reset: DB7 0 32 DB6 0 DB5 1 DB4 1 DB3 1 DB2 0 DB1 0 DB0 0 Data Sheet S13231EJ1V0DS00 PD16314 10.7 CGRAM Address Setting RS Code 0 R,/W 0 DB7 0 DB6 1 DB5 A DB4 A DB3 A DB2 A DB1 A DB0 A This instruction: (1) Loads a new 6-bit address into the address counter. (2) Sets the address counter to point to CGRAM. Once the CGRAM data write instruction has been executed, the value of the address counter (AC) will be automatically incremented (+1) or decremented (-1), as determined by the entry mode setting instruction. The CGRAM address is moved from 3FH to 00H (+1, increment setting) or from 00H to 3FH (-1, decrement setting). After reset: Don't care. 10.8 DDRAM address setting RS Code 0 R,/W 0 DB7 1 DB6 A DB5 A DB4 A DB3 A DB2 A DB1 A DB0 A This instruction: (1) Loads a new 7-bit address into the address counter. (2) Sets the address counter to point to DDRAM. Once the DDRAM address setting has been executed once, the contents of the address counter (AC) will be automatically incremented (+1) or decremented (-1) after every access of DDRAM, as determined by the entry mode setting instruction. Table 10-3. Valid DDRAM Address Range - Number of Characters 1st line 2nd line 40 40 Address Range 00H to 27H 40H to 67H After reset: Don't care. 10.9 Reading Busy Flag and Address RS Code 0 R,/W 1 DB7 BF DB6 A Note DB5 A DB4 A DB3 A DB2 A DB1 A DB0 A This instruction reads the busy flag (BF) and the value of the address counter in binary "AAAAAAA". This address counter is used by the CGRAM and DDRAM addresses, and its value is determined by the previous instruction. The address counter contents are same as for the CGRAM address setting and DDRAM address setting instructions. Note The busy flag (BF) always outputs 0. Data Sheet S13231EJ1V0DS00 33 PD16314 10.10 Writing Data to CGRAM or DDRAM RS Code 1 R,/W 0 DB7 D DB6 D DB5 D DB4 D DB3 D DB2 D DB1 D DB0 D High-order bits This instruction writes 8-bit binary data "DDDDDDDD" to CGRAM or DDRAM. Low-order bits Whether to write to CGRAM or DDRAM is determined by the following instruction of CGRAM address setting or DDRAM address setting. After a data write, the value address is automatically incremented or decremented by 1 according to the entry mode set. The entry mode also determines the display shift. 10.11 Reading Data from CGRAM or DDRAM RS Code 1 R,/W 1 DB7 D DB6 D DB5 D DB4 D DB3 D DB2 D DB1 D DB0 D High-order bits This instruction reads 8-bit binary data "DDDDDDDD" from CGRAM or DDRAM. Low-order bits The previous specification determines whether CGRAM or DDRAM is to be read. Before entering this instruction, either the CGRAM address setting or the DDRAM address setting instruction must be executed. If neither is executed, the first read data is invalid, so when consecutively executing read instructions, the next address data is normally read from the second read. The address setting instructions do not need to be executed just before this read instruction, when the cursor is shifted by the cursor or display shift instruction (only when reading out data from DDRAM). The operation of the cursor shift instruction is the same as the DDRAM address setting instruction. After reading one data, the value of the address is automatically incremented or decremented by 1 according to the entry mode selection. Caution The address counter is automatically incremented or decremented by 1 after the data write instruction to CGRAM or DDRAM is executed. However, even if the contents of the RAM to be data read instruction is executed indicated by the address counter cannot be read. Therefore, to read the data correctly, execute the address setting instruction or the cursor shift instruction (only in the case of DDRAM data read) just before reading, or, read from the second data in the case of executing the consecutive read data instruction. 34 Data Sheet S13231EJ1V0DS00 PD16314 10.12 Power On Reset The Internal status of PD16314 is initialized as follows after the power supply is turned on. (1) Display clear: DDRAM is filled with 20H (space code). (2) The address counter is set to 00H. The address counter is set to point to DDRAM. (3) Display ON/OFF: D = 0, C = 0, B = 0 (4) Entry mode set: I/D = 1, S = 0 (5) Function set: DL = 1, N = 1 (6) Brightness adjustment: BR0 = BR1 = 0 (7) The CPU interface and duty ratio selection are based on Table 10-4. Table 10-4. Relationship between Status of PD16314 and Pin Selection at Power on Reset - Pin Name TEST H L or open L or open L or open L or open L or open L or open IM x L H x x x x DS1 x x x L L H H DS0 x x x L H L H Self test mode Serial interface Parallel interface Duty = 1/16 (16C x 1 or 2L display) Duty = 1/20 (20C x 1 or 2L display) Duty = 1/24 (24C x 1 or 2L display) Duty = 1/40 (40C x 1 or 2L display) SI,SO, SCK, STB used RS, E, R,/W, DB7 to DB4, or DB7 to DB0 used The extension driver does not need to be used. The number of lines is selected by insutruction. The extension driver should be used. The number of lines is selected by instruction. Function Remark Remark X: Don't care Data Sheet S13231EJ1V0DS00 35 PD16314 11. EXAMPLE OF DATA TRANSFER (8-bit Parallel, Data Increment Mode) Figure 11-1. Initialization and Data Setting Procedure - Power ON All registers set to initialized value. Function setting Set data length, display line number and display brightness. CGRAM address setting Data write Write the data to CGRAM. End of data write Yes DDRAM address setting No Data write Write the data to DDRAM. End of Data write Yes Display ON/OFF No Display ON Table 11-1. Example of Initialization and Data Setting (M68 Series CPU) - RS 0 R,/W 0 D7 0 D6 0 D5 1 D4 1 D3 1 D2 x D1 0 D0 1 Function setting Data length: 8 bits, Display line number: 2 lines VFD brightness: 75% CGRAM address set to 00H Write data to CGRAM 64 bytes (8 characters) Power ON 0 1 0 0 0 x x x 1 x x x 0 D D D 0 0 x x x 0 D D D 0 0 D D D 0 D D D 0 0 D D D 0 D D D 1 0 D D D 0 D D D 1 0 D D D 0 D D D 0 0 D D D 0 D D D 0 0 1 0 0 1 D D D DDRAM address set to 00H Write data to DDRAM 80 bytes (80 characters) 0 0 0 Display ON, cursor OFF, cursor blink OFF 36 Data Sheet S13231EJ1V0DS00 PD16314 12. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 C, VSS1 = VSS2 = 0 V) Parameter Logic power supply voltage Logic input voltage Logic output voltage Driver power supply voltage Driver output voltage Driver output current Anode Symbol VDD1 VI VO1 VDD2 VO2 IOL2A IOH2A Grid IOL2G IOH2G Allowable loss Operating ambient temperature Storage temperature PD TA Tstg Rating -0.5 to +6.0 -0.5 to VDD1 + 0.5 -0.5 to VDD1 + 0.5 -0.5 to +60 -0.5 to VDD2 + 0.5 10 -2 15 -20 1.2 -40 to +85 -65 to +150 Unit V V V V V mA mA mA mA W C C * * Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA =25 C, VSS1 = VSS2 = 0 V) Parameter Logic power supply voltage Logic system input voltage Driver power supply voltage Driver output current Anode Symbol VDD1 VIN VDD2 IOL2A IOH2A Grid IOL2G IOH2G MIN. 2.7 0 20 TYP. 5.0 MAX. 5.5 VDD1 50 5 -1 8 -15 Unit V V V mA mA mA mA * * Remark NEC recommends that power is applied to the chipset in the order given below. VDD1 Input VDD2 When turning the power off, the reverse order should be applied. Data Sheet S13231EJ1V0DS00 37 PD16314 Electrical Characteristics (Unless otherwise specified, TA = -4 to +85 C, VDD1 = 5.0 V, VDD2 = 50 V, VSS1 = VSS2 = 0 V) -40 Parameter Symbol VIH1 VIL1 VIH2 VIL2 VOH1 Conditions Logic, except E,SCK, /RESET, R,/W Logic, except E,SCK, /RESET, R,/W E,SCK, /RESET, R,/W E,SCK, /RESET, R,/W DBn, SI,SO, SDO, SLK, LE, /CL IO1L = -0.1 mA Low-level output voltage (Logic) VOL1 DBn, SI,SO, SDO, SLK, LE, /CL IO1L = 0.1 mA High-level input current High-level leakage current IIH ILOH ILOL -Ip VOH2A1 VOH2A2 VOH2G Low-level output voltage (Driver) VOL2 IDD1 IDD2 TEST, VIN = VDD1 Logic, VIN/OUT = VDD1 Logic, except DBn, SI, SO DBn, SI, SO A1 to A80, IOH2 = -0.5 mA A1 to A80, IOH2 = -1 mA G1 to G24, IOH2 = -15 mA A1 to A80, G1 to G24, IOL2 = 1 mA Logic (no CPU access) Driver 30 48 46 45 5 100 100 125 20 500 1.0 -1.0 280 VSS1 + 0.5 VDD1 - 0.5 MIN. 0.7 VDD1 TYP. MAX. Unit V * * * * High-level input voltage 1 Low-level input voltage 1 High-level input voltage 2 Low-level input voltage 2 High-level output voltage (Logic) 0.3 VDD1 0.8 VDD1 0.2 VDD1 V V V V V A A A A V V V V * * * * Low-level leakage current Pull-up MOS current High-level output voltage (Driver) * Current consumption A A Remark The TYP. value is a reference value when TA = 25 C. Switching Characteristics (Unless otherwise specified, TA = -40 to +85 C, VDD1 = 5.0 V 10 %) Parameter Oscillation frequency Symbol fOSC fC TTLH1 TTLH2 Fall time TTHL R = 56 k OSCIN external clock A1 to A80, CL = 50 pF G1 to G24, CL = 50 pF A1 to A80, G1 to G24, CL = 50 pF Condition MIN. 392 350 TYP. 560 560 MAX. 728 750 2.5 0.25 1.0 Unit kHZ kHZ * * Oscillation frequency Rise time s s s Remark The TYP. value is a reference value when TA = 25 C. Switching Timing TTHL TTLH1,2 90% 90% Am, Gn 10% 10% 38 Data Sheet S13231EJ1V0DS00 PD16314 Required Conditions for Timing 1 (Unless otherwise specified, TA = -4 to +85 C) -40 Parallel data transfer (M68 interface): Write (VDD1 = 5.0 V 10 %) Parameter Enable cycle time Enable "H" pulse width Enable "L" pulse width RS, R,/W - E setup time RS, R,/W - E hold time Data setup time Data hold time Reset pulse width Symbol tCYCE PWEH PWEL tAS tAH tDS tDH tWRE EE E E RS, R,/W E E RS, R,/W DATA E E DATA Conditions MIN. 500 230 230 20 10 80 10 500 TYP. MAX. Unit ns ns ns ns ns ns ns ns Parallel data transfer (M68 interface): Read (VDD1 = 5.0 V 10 %) Parameter Enable cycle time Enable "H" pulse width Enable "L" pulse width RS, R,/W - E setup time RS, R,/W - E hold time Data delay time Data hold time Symbol tCYCE PWEH PWEL tAS tAH tDD tDHR EE E E RS, R,/W E E RS, R,/W E DATA E DATA 5 Conditions MIN. 500 230 230 20 10 160 TYP. MAX. Unit ns ns ns ns ns ns ns Data Sheet S13231EJ1V0DS00 39 PD16314 Parallel Interface (M68 input) RS R,/W tAS /CS PWEH PWEL tAH E tDS DB0 to DB7 tCYCE Valid Data tDH Parallel Interface (M68 output) RS R,/W tAS /CS PWEH PWEL tAH E tDD DB0 to DB7 tCYCE Valid Data tDHR Remarks 1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. 2. All timing is specified using 20 % and 80 % of VDD1 as the reference. 3. PWEH is specified as the overlap between /CS being L and E. 40 Data Sheet S13231EJ1V0DS00 PD16314 Required Conditions for Timing 2 (Unless otherwise specified, TA = -4 to +85 C) -40 Parallel data transfer (i80 interface): Write (VDD1 = 5.0 V 10 %) Parameter RS hold time RS setup time Symbol tRH8 tRS8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 tWRE /WR /RD /WR /RD DB0 to DB7 DB0 to DB7 DB0 to DB7, CL = 100 pF DB0 to DB7, CL = 100 pF 5 500 A0 A0 Conditions MIN. 10 10 200 30 70 100 100 30 10 70 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns * System cycle time Control "L" pulse width(WR) Control "L" pulse width(RD) Control "H" pulse width(WR) * Control "H" pulse width(RD) Data setup time Data hold time /RD access time Output disable time Reset pulse width Parallel Interface (i80) RS tf /CS tRS8 tCCLR, tCCLW tCYC8 tr tRH8 /WR, /RD tf tCCHR, tCCHW tDS8 tDH8 DB0 to DB7 (Write) tACC8 DB0 to DB7 (Read) tOH8 Remarks 1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. 2. All timing is specified using 20 % and 80 % of VDD1 as the reference. 3. tCCLW and tCCLR are specified as the overlap between /CS being L and /WR and /RD being at the L level. Data Sheet S13231EJ1V0DS00 41 PD16314 Required Conditions for Timing 3 (Unless otherwise specified, TA = -4 to +85 C) -40 Serial data transfer (VDD1 = 5.0 V 10 %) Parameter Shift clock cycle High-level shift clock pulse width Low-level shift clock pulse width Shift clock hold time Data setup time Data hold time STB hold time STB pulse width Wait time Output data delay time Output data hold time Reset pulse width Symbol tCYK tWHK tWLK tHSTBK tDS tDH tDKSTB tWSTB tWAIT tODD tODH tWRE 8th CLK 1st CLK STB DATA SCK DATA 5 500 SCK SCK SCK STB SCK DATA SCK SCK DATA SCK STB Conditions MIN. 500 200 200 100 100 100 500 500 1 150 TYP. MAX. Unit ns ns ns ns ns ns ns ns s ns ns ns Serial Interface (Input) tWSTB STB tHSTBK tWLK tCYK tWHK tDKSTB SCK tDS tDH SI Serial Interface (Output) tWSTB STB tHSTBK tWLK tCYK tWHK tDKSTB SCK tODD tODH SO Remarks 1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. 2. All timing is specified using 20 % and 80 % of VDD1 as the reference. 42 Data Sheet S13231EJ1V0DS00 PD16314 AC Measurement Point VIH Input VOH Output VOL VIL Reset /RESET tWRE Required Conditions for Timing 4 (Unless otherwise specified, TA = -4 to +85 C) -40 Common timing (M68, i80, serial interface): Power ON reset (VDD1 = 5.0 V 10 %) Parameter Resetting time VDD rising time VDD OFF width Symbol tRES trDD tOFF VDD VDD VDD Conditions MIN. 100 1 1 TYP. MAX. Unit s s ms trDD tRES 4.5 V VDD 0.2 V tOFF Internal reset time Data Sheet S13231EJ1V0DS00 43 PD16314 13. PACKAGE DRAWING 144-PIN PLASTIC LQFP (FINE PITCH) (20 20) A B 108 109 73 72 Detail of lead end C D S R Q 144 1 37 36 F G P H I M J K M N NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. L ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 22.00.2 20.00.2 20.00.2 22.00.2 1.25 1.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145 +0.055 -0.045 0.10 1.40.1 0.1250.075 3 +7 -3 1.7 MAX. INCHES 0.8660.008 0.787 +0.009 -0.008 0.787 +0.009 -0.008 0.8660.008 0.049 0.049 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.0060.002 0.004 0.0550.004 0.0050.003 3 +7 -3 0.067 MAX. S144GJ-50-8EU-2 44 Data Sheet S13231EJ1V0DS00 PD16314 * 14. SOLDERING CONDITIONS Solder the product under the following recommended conditions. For details of the recommended soldering conditions, refer to information Document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and soldering conditions other than those recommended, please contact an NEC salesperson. Surface Mount Type PD16314GJ-001-8EU: 144-PIN PLASTIC LQFP (20x20 mm) Soldering Method Infrared reflow Package peak temperature: 235 C, Time: 30 seconds MAX. (210 C MIN.), Number of times: 3 MAX. - Caution Do not use two or more soldering methods in combination (except the partial heating method). Data Sheet S13231EJ1V0DS00 45 PD16314 [MEMO] 46 Data Sheet S13231EJ1V0DS00 PD16314 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S13231EJ1V0DS00 47 PD16314 * The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8 |
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